This repo aims to merge XuanTie-C910 microprocessor with Xilinx FPGA boards such as ZCU102 and Alveo U50. This is one of my part-time hobby and somehow not on on my priority list. Patient, LOL :) $ cd ...

Protocol of input and output are AXI4-Stream IP core made by this code can run close to 1pix/clock because of pipeline processing You can make other image processing module that are like sequential ...